The mobile computing (e.g., smart phone and tablet) markets benefit from smaller component form factors and lower power consumption. Because current platform solutions for smart phones and tablets rely on multiple packaged integrated circuits (ICs) mounted onto a circuit board, further scaling to smaller and more power efficient form factors is limited. For example, a smart phone will include a separate power management IC (PMIC), radio frequency IC (RFIC), and WiFi/Bluetooth/GPS IC, in addition to a separate logic processor IC. System on Chip (SoC) architectures offer the advantage of scaling which cannot be matched by board-level component integration. While the logic processor IC may itself be considered a system on a chip (SoC) integrating both memory and logic functions, more extensive SoC solutions for mobile computing platforms have remained elusive because the PMIC and RFIC operate with two or more of high voltage, high power, and high frequency.
While an SoC solution for the mobile computing space that would integrate PMIC and RFIC functions is attractive for improving scalability, lowering costs, and improving platform power efficiency, one barrier to such an SoC solution is the lack of a scalable transistor technology having both sufficient speed (i.e., sufficiently high gain cutoff frequency, Ft), and sufficiently high breakdown voltage (BV).
Certain non-silicon devices, such as group III-nitride (III-N) devices, offer a promising avenue for integration of PMIC and RFIC functions as both high BV and Ft can be obtained. For such devices, an asymmetric high electron mobility transistor (HEMT) structure where device length between the source and gate (Lsg) is different than device length between the gate and drain (Lgd) may enable a particularly high BV with a low on-state source-to-drain resistance (RON). While the shorter Lsg enables a low RON, a longer Lgd enables a high BY. However, these two device dimensions need to be precisely defined for the devices to be manufacturable in high volume. To date, no technique exists to repeatedly define these device dimensions to different values. Conventional methods rely on alignment of two or more lithographic mask patterning operations and such techniques suffer from high variation of Lgd and Lsg dimensions due to inter-mask alignment tolerances/errors.
Enhancement mode operation also remains a challenge for III-N HEMT devices with thresholds in most designs being less than zero (i.e., depletion mode). Large scale integration of III-N HEMTs thus poses power consumption concerns. Conventional threshold adjustment techniques typically rely on gate recess etches (e.g., single or double recess), but limited etch selectivity may make such techniques unsuitable for high volume manufacturing.